Review of Virtual Memory

• Think of the entire program residing on disk, with the most-used parts of the program in main memory.
• In this way the main memory acts as a cache for the disk.
• The virtual memory (disk memory) is divided into blocks called pages. All of these have the same size.
• A typical page size is 4K.
• The physical memory (main memory) is divided into blocks called frames. These have the same size as the pages.
• Address translation is the conversion of a virtual address to a physical address.
• This is done with a page table.
  • A page table is an array in main memory, each entry containing a frame number and a valid bit.
  • The page number is used as an index into the page table to find the corresponding frame number.
  • If the valid bit is true, the item is in main memory, otherwise it is only on disk (a page fault).
  • Since accessing the page table takes a long time, a TLB is used: a cache for the page table.
• In order for a memory access to be done in one cycle, the following must occur:
  • The logical address must correspond to a physical address (valid bit in page table set).
  • The address translation can be done using the TLB (not needing the page table).
  • The data is found in the L1 cache.
• A logical address looks like this:

       ----------------------------------------------------------------
      |         page number                    |          page offset  |
       ----------------------------------------------------------------
  

  where the number of bits in the page offset is determined by the page size.
• This logical address is converted to a physical address that looks like this:

       -----------------------------------------------------------
      |      frame number                 |         frame offset  |
       -----------------------------------------------------------
  

  where the frame offset is the same as the page offset.
• Once we have the physical address, it can be looked up in the cache.
  Do do this, we rename the bits of the physical address:

       -----------------------------------------------------------
      |      tag                       | index |   block offset   |
       -----------------------------------------------------------
  

• The number of bits in the block offset and index are determined by the properties of the L1 cache.
• To look up something in the L1 cache:
  1. first we need to read the tags of the set (given by the index).
  2. next we need to compare all of the tags of that set to the tag in the physical address.
  3. If a match is found, we can read the data from the cache.
• If the index and block offset bits are part of the frame offset, then we can do the first step above in parallel with accessing the TLB. This speeds up the memory access.

Example:
Suppose virtual addresses are 32 bits, physical addresses are 35 bits, and the page size is 4K.
A 16K 4-way set associative cache with a block size of 32 bytes is used.
A logical address looks like:

     ------------------------------------------------------------
    |         page number:20 bits        |  page offset: 12 bits |
     ------------------------------------------------------------

and a physical address looks like:

     ----------------------------------------------------------------
    |        frame number:23 bits            | frame offset: 12 bits |
     ----------------------------------------------------------------

The cache has 16K/32 = 512 blocks and 128 sets, so the physical address also looks like:

                                                 index    block offset
     -----------------------------------------------------------------
    |         tag: 23 bits                   |   7 bits   | 5 bits   |
     -----------------------------------------------------------------

Since the page offset and the frame offset are identical, the index can be determined before the address translation is done.
The first step of the cache lookup can be done in parallel with the accessing of the TLB to do the address translation.

---