Interactive Tomasulo Speculative Execution Coding Form
This is an alpha version under development.
Cycle: unknown

   Max cycle:
Change:
Architecture
Number of Reservation Stations Number of Units Latency
loadstorefaddfmul FP addFP mult loadfaddfmulfdiv
5 5 3 2 1 1 1 2 10 40
Functional units become ready on the cycle after the result is put on the CDB.
Reservation stations become ready on the cycle after the result is put on the CDB.
The second memory reference has a cache miss with a penalty of 6 cycles.

Instruction Summary
Instruction Reservation
Station		 Execution
Unit		 Issue Ex Start Ex End Memory CDB Commit Dest

Reorder Buffer
Entry Busy Instruction          State       Dest Value             

Reservation Stations
Name       Busy         Op                 Vj                       Vk                Qj        Qk        Dest        A   
Load1 
Load2 
Add1 
Add2 
Mult1 
Mult2 

Register Status
Field F0     F2     F4     F6     F8     F10     F12     F14    
Reorder #
Cycle: Unknown
This is the Debug Area
No debug Info.