CS 3853 Computer Architecture Chapter 3 Section 5 Loop Example

Instruction			Reservation Station	Execution Unit	Issue Cycle	Ex Start Cycle	Ex End Cycle	Memory Cycle	CDB cycle	Write dest
1.	L.D	F0,0(R1)	Load1	ALU	1	2	2	3	4	F0
2.	ADD.D	F4,F0,F2	Add1	fadd	2	5	6		7	F4
3.	S.D	F4,0(R1)	Store1	ALU	3	4	4	8		0(R1)
4.	L.D	F6,-8(R1)	Load2	ALU	4	5	5	6	8	F6
5.	ADD.D	F8,F6,F2	Add2	fadd	5	9	10		11	F8
6.	S.D	F8,-8(R1)	Store2	ALU	6	7	7	12 or 13		-8(R1)
7.	L.D	F10,-16(R1)	Load3	ALU	7	8	8	9	10	F10
8.	ADD.D	F12,F10,F2	Add3	fadd	8	11	12		13	F12
9.	S.D	F12,-16(R1)	Store3	ALU	9	10	10	14		-16(R1)
10.	L.D	F14,-24(R1)	Load4	ALU	10	11	11	12 or 13	14	F14
11.	ADD.D	F16,F14,F2	Add4	fadd	11	15	16		17	F16
12.	S.D	F16,-24(R1)	Store4	ALU	12	13	13	18		-24(R1)
13.	DADDUI	R1,R1,#32	Iadd1	ALU	13	14	14		15	R1
14.	BNE	R1,R2,loop	Branch	ALU	14	16	16

Note 1: Instruction 4 is ready with its result on cycle 7, but the CDB is busy.
Note 1a: Instruction 10 is ready with its result on cycle 13, but the CDB is busy.
Note 1b: Instructions 6 and 10 are accessing data memory on the same cycle.
Whether we give preference by issue time or for reads over writes, instruction 10 puts its result on the CDB on cycle 14, since the CDB is not available on cycle 13.
Note 2: The branch cannot execute until R1 is available, after cycle 15.
Note 3: We delay executing instructions until the branch completes, so the next instruction can start execution at cycle 17.
This is equivalent to issuing at 16, so the loop effectively takes 15 cycles, with a cycles per iteration of 3.75.
If the branch is taken, we will need to refetch the next instruction in cycle 17, so the 4 iterations take one cycle longer, for and average of 4.00.
Compare this with the summary from section 2: