There will not be a quiz in this recitation.
In this recitation you will do some review questions for the final exam.

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Problems

1. If machine performance improves by 35% per year, by what percentage will it have improved after 10 years?
2. If machine A is 30% faster than machine B and machine A is 60% faster than machine C, how much faster is machine B than C?
3. If machine performance has improved by a factor of 1,000 over 10 years, at what percentage did it increase each year, assuming that each year had the same percentage increase?
4. A system has 5 disk drives, each with a MTTF of 500,000 hours, and a single power supply with a MTTF of 200,000 hours. The system will fail if one component fails. Calculate the system MTTF.
5. If we reduce the CPI from 5 to 4 while increasing the clock cycle from 1 ns to 1.1 ns, what is the speedup?
6. Processors A and B are identical, except that processor B executes floating point instructions 40% faster than A. Calculate the speedup if a task spends 20% of its time executing floating point instructions on machine A.
7. Processors A and B are identical, except that processor B executes floating point instructions 40% faster than A. Calculate the speedup if a task spends 20% of its time executing floating point instructions on machine B.
8. Suppose that a cache has a hit time of 1 cycle, a hit ratio of 92%, and a miss penalty of 8 cycles. What is the average access time in cycles?
9. Suppose we have a standard MIPS 5-stage pipeline which has a CPI of 1 when all memory accesses are cache hits. A cache is used with a hit rate of 95% and a miss penalty of 8 cycles. Loads and stores are 30% of all instructions. What is the CPI when cache misses are taken into account?
10. A memory system uses three caches. The hit rates and hit times are as follows:
    • L1: .95, 1 ns.
    • L2: .98, 6 ns.
    • L3: .99, 20 ns.
    For a memory access, first the L1 cache is checked, If there is a miss, the L2 cache is checked. If there is a miss in the L2 cache, the L3 cache is checked. Finally, a miss in the L3 cache causes an access to main memory which has an access time of 60 ns. What is the effective memory access time?

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The following are from a previous recitation which may not have been completed.

11. Fill in the following table to illustrate how Tomasulo's algorithm works.
    Assume the following:
    • There are sufficient reservation stations.
    • There is only one functional unit that does both floating point add and subtract.
    • There is only one functional unit that does multiply and divide.
    • Execution times are as follow: load: 1, fadd: 2, fsub: 2, fmul:5, fdiv: 10
    • The L.D execution is the address calculation that uses dedicated hardware that can do the calculation in one cycle.
    • Floating point units (fadd and fmul) are busy during execution and can be reused the cycle after execution completes.
      This is different from the assumption we made in lecture.
    • If two reservation stations are both ready and competing for the same functional unit, the one that issued first has priority.
    
    

    Instruction		Reservation Station	Execution Unit	Issue Cycle	Ex Start Cycle	Ex End Cycle	Memory Cycle	CDB cycle	Write dest
    L.D	F0,8(R2)
    ADD.D	F4,F2,F2
    SUB.D	F6,F4,F0
    MUL.D	F10,F2,F4
    ADD.D	F12,F2,F4
    SUB.D	F14,F10,F0

    
    
12. Redo problem 11 assuming that there are 2 functional units that can add and subtract.
13. Redo problem 11 assuming that the first instruction has a cache miss with a miss penalty of 10 cycles.
14. Redo problem 11 assuming that there is only 1 add reservation station which is reserved until the cycle after the result is put the the CDB.