There will not be a quiz in this recitation.
There will be an exam in class on Thursday of this week.
The exam will cover the material from Appendix B.
The following problems are review problems for the exam.
The first 7 of these questions are left over from the previous week.
- A 64KB direct mapped cache has a block size of 128 bytes. How many bits of a 32-bit address are used for the
block offset, index, and tag.
- Repeat the above problem for a 2-way set associative cache.
- Repeat the above problem for a fully associative cache.
- What is the minimum number of bits per entry needed to implemented LRU for a fully associative 64 KB cache with
a block size of 32 bytes?
- What is the purpose of using a dirty bit in each entry of a write-through cache?
- Which is better, a CPI of 1.21 with a clock cycles time of .4 ns, or a CPI of 1.32 with a clock cycle if .38 ns.? Explain.
- A memory system uses 2 caches, an L1 cache with a hit rate of .95 and a hit time of .5 ns, and an L2 cache with a
hit rate of .99 and a hit time of 1.3 ns. The main memory access time is 20 ns.
First the L1 cache is checked. If a miss occurs the L2 cache is checked. A miss in the L2 cache causes an access to
main memory. What is the effective memory access time?