There will be a quiz in this recitation.
It will be a closed book exam. You may not use a computer.
You may bring a calculator that can do add, subtract, multiply, divide, powers (y^x), and logs.
The quiz will consist of three questions and each problem is worth 3 points:

• 1 point for turning in the paper
• 2 points for showing some reasonable work
• 3 points for showing work and getting the correct answer

The first problem on the quiz will be about the fields of a memory address used for cache lookups.
The other problems will involve calculating a miss ratio for a unified cache given the miss rate per access or per instruction.

After turning in the quiz, start on the problems below.
The first 5 of these are carried over from Recitation 6.

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1. Redo problem 3 from Recitiation 6 for a block size of 256 bytes.
2. Suppose you have a 32KB direct mapped cache with a 32-byte block.
   1. How many bits of an address are used for the block offset?
   2. How many bits of an address are used for the index?
   3. How many bits of an address are used for the tag?
3. Repeat the above problem for a 2-way set associative cache.
4. Repeat the above problem for a 4-way set associative cache.
5. Repeat the above problem for a fully associative cache.
6. An L1 cache has a hit ratio of 90%, a hit time of 1 ns, and a miss penalty of 50 ns. What is the effective memory access time?
7. An L2 cache with a hit rate of 90% and a hit time of 5 ns is added to the above L1 cache. What is the effective memory access time?
8. A memory system uses three caches. The caches have hit rates and times given. Main memory has an access time of 50 ns. For a memory access, first the L1 cache is checked. If there is a miss, the L2 cache is checked. If there is a miss in the L2 cache, the L3 cache is checked. Finally, a miss in the L3 caches causes an access to main memory. What is he effective memory access time?

   Cache	hit rate	hit time
   L1	.90	1 ns.
   L2	.95	5 ns.
   L3	.97	10 ns.