CS 3853 Computer Architecture Recitation 4 Answers Fall 2013

Current Practice Problems

    1. Without forwarding, R1 is not ready in the register file until the beginning of the 5th cycle of the DADD, and it is needed at the end of the second cycle of the DSUB. Two cycles of stall are needed in DSUB. No additional stalls are needed for the AND.
      With forwardings, R1 is available third cycle of DADD and is not needed until the third cycle of DSUB, so no stalls are needed.
    2. Without forwarding, this is similar to the previous example so 2 stall cycles are needed. With forwarding, R1 is available at the end of the 4th cycle of LD and is needed at the beginning of the third cycle of DSUB, so one stall cycle is needed.
  2. Move the AND instruction up one so that it is executed between the LD and the AND.
    1. This designates the rs register, R2, so the value is 2.
    2. This designates the rt register, R1, so the value is 1. Note that this is not used.
    3. This designates the destination register, R1, so the value is 1.
    4. This is the value written back to the register file which is R2 + 5 = 18.
    5. The value of R2 is 13.
    6. The value of R1 is 9. (This is not used.)
    7. 5
    8. The bottom input, corresponding to A.
    9. The bottom input, corresponding to Imm.
      10. A
    10. The result of the instruction which is R2 + 5 = 18.
    11. 0
    12. The top input corresponding to NPC = PC + 4.
    13. The bottom input corresponding to ALU output.
    1. MEM
    2. EX
    3. ID
    4. This is for the DSUB instruction so the inputs are R5 and R6 which are 21 and 23.
    5. This is for the DADD instruction so the inputs are R2 and R3 which are 15 and 17.
    6. This is for the AND instruction so the inputs are R8 and 40 which are 27 and 40.
    7. This is for the AND instruction, so the rs field represents R8, so the value is 8.
    8. This is for the AND instruction, so the rt field represents R7, so the value is 7.
    9. This input comes from the MEM/WB register so it corresponds to the instruction in the WB phase during cycle i+4, which is the DADD instrution.
      It represents the destination register which is R1, to the value is 1.

Practice Problems for Pipeline Forwarding

  1.   instruction cycle 1  cycle 2  cycle 3  cycle 4  cycle 5  cycle 6  cycle 7  cycle 8  cycle 9  cycle 10 
     LD   R1, 8(R2) IFIDEXMEMWB
     DSUB R4, R5, R6 IFIDEXMEMWB
     AND  R7, R8, R9 IFIDEXMEMWB
  2.   instruction cycle 1  cycle 2  cycle 3  cycle 4  cycle 5  cycle 6  cycle 7  cycle 8  cycle 9  cycle 10 
     LD   R1, 8(R2) IFIDEXMEMWB
     DSUB R4, R1, R2 IFstallstallIDEXMEMWB
     AND  R5, R1, R7 stallstallIFIDEXMEMWB
  3.   instruction cycle 1  cycle 2  cycle 3  cycle 4  cycle 5  cycle 6  cycle 7  cycle 8  cycle 9  cycle 10 
     LD   R1, 8(R2) IFIDEXMEMWB
     DSUB R4, R1, R2 IFstallIDEXMEMWB
     AND  R5, R1, R7 stallIFIDEXMEMWB

Practice Problems for Chapter 1

  1. (1.3)50 = 497,929, so it increases by 4978%.
  2. 1.4 × 1.7 = 2.38, so A is 138% faster than C.
  3. EB/EA = 1.4 and EC/EA = 1.8, then EC/EB = 1.8/1.4 = 1.2857, so B is 28.57% faster than C.
  4. x20 = 5000 so 20 log x = log 5000. Using base 10, log x = 3.699/20 = .1849, so x = 1.53. 53% per year.
  5. failure rate = 4/1,000,000 + 2/600,000 = 7.333 × 10-6, so the MTTF = 136,364.
  6. For 6 2TB drives the MTTF is 1,000,000/6 = 166,667 hours and for 3 4TB drives the MTTF is 600,000/3 = 200,000, so using the 4TB drives has the better MTTF.
  7. 1/(.4 + .6/2) = 1/.7 = 1.4286
  8. Enew = .4 × Enew + .6 × Enew
    Eold = .4 × Enew + .6 × 2 × Enew = 1.6 × Enew, so
    Eold/Enew = 1.6
  9. EA = .4 × EA + .2 × EA + .4 × EA
    EB = .4 × 1.3 × EA + .2/1.5 × EA + .4 × EA = 1.0533 × EA
    so EB/EA = 1.0533 and A is 5.33% faster than B.
  10. 1.5 = 1/(.5 + .5/s) gives s = 3