CS 3853 Computer Architecture Chapter 3 Section 4 Example Answers

Modification 9: fmul takes 5 cycles instead of 10

Instruction		Reservation Station	Execution Unit	Issue Cycle	Ex Start Cycle	Ex End Cycle	Memory Cycle	CDB cycle	Write dest
L.D	F6,32(R2)	Load1	ALU	1	2	2	3	4	F6
L.D	F2,44(R3)	Load2	ALU	2	3	3	4	5	F2
MUL.D	F0,F2,F4	Mult1	fmul	3	6	10		11	F0
SUB.D	F8,F2,F6	Add1	fadd	4	6	7		8	F8
DIV.D	F10,F0,F6	Mult2	fmul	5	12	51		52	F10
ADD.D	F6,F8,F2	Add1	fadd	6	9	10		12	F6

Note 1: The MUL.D finishes 5 cycles earlier so the DIV.D can start 5 cycles earlier.
Note 2: The ADD.D cannot put the result on the CDB in cycle 11 since the CDB is not free.