CS 3853 Computer Architecture Chapter 3 Section 4 Example Answers

Modification 7: The second memory access is a cache miss with a penalty of 6 cycles

Instruction		Reservation Station	Execution Unit	Issue Cycle	Ex Start Cycle	Ex End Cycle	Memory Cycle	CDB cycle	Write dest
L.D	F6,32(R2)	Load1	ALU	1	2	2	3	4	F6
L.D	F2,44(R3)	Load2	ALU	2	3	3	4-10	11	F2
MUL.D	F0,F2,F4	Mult1	fmul	3	12	21		22	F0
SUB.D	F8,F2,F6	Add1	fadd	4	12	13		14	F8
DIV.D	F10,F0,F6	Mult2	fmul	5	23	62		63	F10
ADD.D	F6,F8,F2	Add2	fadd	6	15	16		17	F6

Note 1: The instruction accesses memory on cycle 10 instead of cycle 4 and puts the result on the CDB in cycle 11.
Note 2: The MUL.D and SUB.D cannot start executing until F2 is available in cycle 12.