CS 3853 Computer Architecture Chapter 3 Section 4 Example Answers

Modification 6: The instruction ADD.D F0,F4,F4 is executed at the end of this code. When does it complete?

Instruction		Reservation Station	Execution Unit	Issue Cycle	Ex Start Cycle	Ex End Cycle	Memory Cycle	CDB cycle	Write dest
L.D	F6,32(R2)	Load1	ALU	1	2	2	3	4	F6
L.D	F2,44(R3)	Load2	ALU	2	3	3	4	5	F2
MUL.D	F0,F2,F4	Mult1	fmul	3	6	15		16	F0
SUB.D	F8,F2,F6	Add1	fadd	4	6	7		8	F8
DIV.D	F10,F0,F6	Mult2	fmul	5	17	56		57	F10
ADD.D	F6,F8,F2	Add2	fadd	6	9	10		11	F6
ADD.D	F0,F4,F4	Add3	fadd	7	12	13		14	F0

Note: The instruction can issue in cycle 7, but the fadd is not available until cycle 9. At cycle 9 the previous add has priority and starts executing at cycle 9.