CS 3853 Computer Architecture Chapter 3 Section 5 Loop Example

Instruction			Reservation Station	Execution Unit	Issue Cycle	Ex Start Cycle	Ex End Cycle	Memory Cycle	CDB cycle	Write dest
1.	L.D	F0,0(R1)	Load1	ALU	1	2	2	3	4	F0
2.	ADD.D	F4,F0,F2	Add1	fadd	2	5	6		7	F4
3.	S.D	F4,0(R1)	Store1	ALU	3	4	4		8	0(R1)
4.	L.D	F6,-8(R1)	Load2	ALU	4	5	5	6	9	F6
5.	ADD.D	F8,F6,F2	Add2	fadd	5	10	11		12	F8
6.	S.D	F8,-8(R1)	Store2	ALU	6	7	7		13	-8(R1)
7.	L.D	F10,-16(R1)	Load3	ALU	7	8	8	9	10	F10
8.	ADD.D	F12,F10,F2	Add3	fadd	8	11	12		14	F12
9.	S.D	F12,-16(R1)	Store3	ALU	9	10	10		15	-16(R1)
10.	L.D	F14,-24(R1)	Load4	ALU	10	11	11	12	16	F14
11.	ADD.D	F16,F14,F2	Add4	fadd	11	17	18		19	F16
12.	S.D	F16,-24(R1)	Store4	ALU	12	13	13		20	-24(R1)
13.	DADDUI	R1,R1,#32	Iadd1	ALU	13	14	14		17	R1
14.	BNE	R1,R2,loop	Branch	ALU	14	18	18

Note 1: Instruction 4 is ready with its result on cycle 7, but the CDB is busy. At cycle 8, Instruction 3 has its result ready and puts it on the CDB. Instruction 4 has to wait until cycle 9.
Note 2: The branch cannot execute until R1 is available, after cycle 18.
Note 3: We delay executing instructions until the branch completes, so the next instruction can start execution at cycle 19.
This is equivalent to issuing at 18, so the loop effectively takes 17 cycles, with a cycles per iteration of 4.25.
Compare this with the summary from section 2: