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Read Appendix B.5

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Today's News: October 29, 2012

Next exam: November 9

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B.5: Virtual Memory Protection and Examples

We will concentrate on the paged virtual memory examples and skip the segmentation examples.

The 64-bit Opteron Memory Management

• Supports page sizes of 4K, 2MB, and 4MB
• We will look at the 4K page
• Uses up to 64-bit virtual addresses and up to 52 bit physical addresses
• We will look at an example that uses a 48-bit virtual address and a 40-bit physical address
• How much memory can be addressed by 40 bits? 1024 gigabytes
• A 48-bit virtual address with a 4K page size would have page tables with 64 billion entries.
• To manage these sizes, uses a 4-level translation of virtual address to physical address.
• Figure B.27 shows how a 48-bit virtual address is mapped into a physical address.
• Each page table entry is 64 bits (8 bytes) and has 512 entries for a total of 4K (the page size).
• A frame number is 40 bits - 12 bits = 28 bits.
• Each page table entry contains a frame number and some protection bits.
• Protection bits include
  • presence (valid)
  • read/write
  • user/superuser
  • dirty
  • accessed
  • no execute
• Separate TLBs are used for instruction and data translation, each with 2 levels
  • block size: 1 PTE (page table entry of 8 bytes)
  • block selection: LRU
  • other parameters:

    	hit time	size	placement
    L1	1 cycle	40 entries	fully associative
    L2	7 cycles	512 entries	4-way set associative

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Another Example

Figure B.25 shows the first two levels of a 64-bit memory system.

• virtual address: 64 bits
• physical address: 41 bits
• page size 8KB
• TLB: direct mapped with 256 entries
• L1 cache: 8KB direct mapped, block size 64 bytes: 128 blocks
• L2 cache: 4MB direct mapped, block size 64 bytes: 64K blocks

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