CS 3733 Operating Systems Notes: Virtual Memory Examples

Real Page Tables

Real page tables often contain information in addition to a valid bit and a frame number. Some typical bits include:

• dirty: indicates that the page has changed since it was read from disk
• read-only: an interrupt is generated if a write is performed
• execute: if not set, code cannot be executed from this page
• cache-disabled: if set, do not put this in the cache
• guard: any access to this page generates an interrupt

Real page tables often have several levels:

• A 4K page in a 32-bit address space requires 2²⁰=1Meg page table entries.
• If page table entries are 4 bytes, this is 4 MB of memory.
• Recall that traditional page tables must be in contiguous physical memory.
• This problem is usually solved with multi-level page tables.
• A logical address has three parts, for example:

       -------------------------------------------------------------
      | Level 1: 10 bits   | Level 2: 10 bits    |  Offset: 12 bits |
       -------------------------------------------------------------
  

• The Level 1 page table is locked in physical memory.
• The MMU contains the physical address of the start of the Level 1 page table
• The level 1 page number is an index into the level 1 page table.
• Two different implementations for the level 1 page table entries:
  • Level 1 page table entries contain logical addresses.
    Each is the logical address of a level 2 page table.
    The level 2 page table address also needs to be translated.
    The TLB saves us from an infinite loop of translations.
    Not all of the second level page table needs to be in memory.
  • Level 1 page table entries contain physical addresses.
    This will usually be a frame number and a valid bit.
    On some systems a clear valid bit indicates an invalid memory access.
    On others, it means that the second level page table is on disk.
• In either case, the second level page tables do not need to take up contiguous memory locations.
• The level 2 page number is an index into a level 2 page table.
• The level 2 page table entries contain frame numbers (and valid bit, etc.)
• If no TLB, this takes at least 3 physical memory accesses to access one logical address.
• Here is a picture.

Address Translation in 32-bit Pentium processors

• 32-bit virtual addresses
• Page size = 4K
• Pages not in physical memory are in a paging file on disk.
• Part of the virtual address space (usually 2G) shared by all processes and used for kernel mode.
• Memory allocation done in 2 steps:
  reserve a portion of the virtual address space is reserved
  commit space is allocated in the paging file
• Memory protection:
  read only
  read-write
  execute only
  guard page - generates an exception when accessed
  copy on write - for efficient sharing of memory
• Address translation for a process is in 2 stages:
  A page directory contains 1024 references to page tables (4-bytes, contains the frame number of a page table)
  A page table contains 1024 page table entries (4 bytes each containing a frame number and several dedicated bits)
  Dedicated bits include: dirty, accessed, read-only, valid
  Note how the numbers combine: 1K*1K*4K = 4G
  Virtual address looks like this:

       -------------------------------------------------------------
      |    PDE: 10 bits    |   PTE: 10 bits      |  Offset: 12 bits |
       -------------------------------------------------------------
  

• Only the page directory (1 page) must remain in memory.

Address Translation in the Alpha AXP Model 21064 64-bit virtual address (43 bits used)
64-bit page table entries
8K page size
Virtual address:

              2               10       10        10        13
             ---------------------------------------------------
            |seg| unused | Level 1 | Level 2 | Level 3 | Offset |
             ---------------------------------------------------

• MMU holds physical address of L1 page table.
• L1 page table is locked in memory.
• L1 page table entries contain virtual address of L2 page table.
• L2 page table entries contain virtual address of L3 page table.
• L3 page table entries contain:
  • physical frame number (32 bits).
  • 5 protection fields:
        valid
        user read enable
        kernel read enable
        user write enable
        kernel write enable
    
• A page fault can occur when accessing L2 and L3 page tables.
• Each page table is 1K entries (10 bits), each entry is 8 bytes
• Each page table fits in one page of memory.
• TLB: 32 entries for data, 8 entries for instructions
• hit time: 1 cycle
• miss penalty: about 20 cycles
• physical addresses limited to 34 bits
• Here is a picture.

Traditional Unix Page Replacement

• Called Global Clock Least Recently Used
• Like Second Chance, but does not require a reference bit
• Non-kernel memory is swept in a circular fashion by a software clock hand
• When the clock hand reaches a given frame, the page table entry is located
  • This requires an inverted page table
  • An inverted page table is an array with one entry per frame containing a pid and a page number.
  • If frame is free, do nothing
  • If frame is being used by a pending I/O instruction, do nothing
  • If frame is valid in some page table, mark it invalid but keep the association with the page.
  • If frame is associated with a page but marked invalid in page table, free the frame (no longer associated with the page).
• The clock is controlled by the pagedaemon, process 2.
• The pagedaemon spends most of its time sleeping.
• It wakes up when the number of free frames is below lotsfree.
• If this needs to be done too often, the swapper activates.
• When a page fault occurs, the handler checks to see of the correct frame is still associated with that page. If so, the valid bit is set true and the process can continue without losing the CPU.
• The above situation is called a "soft page fault". This will have a penalty of less than a microsecond instead of a few milliseconds.

Page Replacement in Solaris

• When a page fault occurs, a frame from the free frame list is assigned.
• Must keep a large number of free frames.
• If number of free pages falls below lotsfree the pageout process executes.
• lotsfree is typically about 1/64 of total physical memory.
• pageout is similar to second chance.
• The algorithm is known as the clock or 2-handed clock algorithm.
• It uses both a hardware reference bit and a dirty bit, both kept in the MMU.
• The first hand scans all frames setting the reference bit to 0.
• A second hand runs behind the first one. If it finds a reference bit is 0, it frees the frame. If the dirty bit is set, the corresponding page must be written back to memory.
• The distance between the hands is called the handspread and the rate of scanning is called the scanrate (in frames per second). They determine how often a page needs to be referenced to be kept in memory.
• The scanrate can range from 100 frames per second to 8192 frames per second.
• If pageout cannot keep enough frames free, some processes are removed from memory (swapping).

Page Replacement in Win 2000 and Win XP

• Maintain a substantial number of free pages.
• This means that a page fault can be satisfied by a single disk access, a read.
• The major part of the algorithm is how pages are taken away from processes and given to the free list.
• Each process has a working set described by two parameters, min and max.
• Here the "working set" means the number of frames allocated to the process.
• These are not hard limits and a process may have fewer frames than min or more than max.
• Each process starts with the same min and max, but these may change over time.
• min is typically 20-50 and max is typically 45-345, depending on total ram.
• If a page fault occurs and the working set is smaller than the max, a page is added.
• If it is larger than the max, a page is removed, but stays in memory.
• Once a second, the balance set manager checks if there are enough free frames.
• If not it starts the working set manager to recover more frames, starting with large processes that have been idle for a while.
• Each page is examined.
• Each page has a counter associated with it:
  if reference bit is set, counter is cleared
  if reference bit is clear, counter in incremented
  pages with highest counters are removed
• Reference bit is part of the CPU, so this is only used for uniprocessors.
• On multiprocessors, FIFO is used.
• There are 4 free lists:
  standby: contain clean pages that can be restored to processes
  modified: contain dirty pages that can be restored to processes
  free: contain frames not associated with a process
  zeroed: these are free and contain 0's
  
• There is also a list of physically bad RAM frames
• Standby and modified lists allow for fast (soft) page faults.