CS 3853 Computer Architecture Recitation 12 Answers Fall 2013

Answers to problems
  1. (1.35)10 = 20.11 = 1 + 19.11, so this is an increase of 1911%
  2. EB/EA = 1.3 and EC/EA = 1.6, so EC/EB = 1.6/1.3 = 1.23, so B is 23% faster than C.
  3. (1 + x)10 = 1000, so 10 log10(1 + x) = log101000 = 3, so 10 log10(1 + x) = log101000 = 3, so log10(1 + x) = .3, so 1 + x = 10.3 = 1.9952, so x = .9952, and the increase is 99.52%.
  4. failure rate = 5/500,000 + 1/200,000 = 3/200,000, so the MTTF is 200,000/3 = 66,667 hours.
  5. Time per instruction was 5 ns. New time per instructions is 4.4 ns. The speedup is 5/4.4 = 1.136
  6. EA = .8 + .2 and EB = .8 + .2/1.4 = .94286, so the speedup is EA/EB = 1/.94286 = 1.0606
  7. EB = .8 + .2 and EA = .8 + .2(1.4) = 1.08, so the speedup is EA/EB = 1.08
  8. 1 + .08(8) = 1.64
  9. An instruction has an average number of memory accesses of 1.3 (since each instruction has a fetch).
    CPI = 1 + (1.3)(.05)(8) = 1.52
  10. average access time is 1 + .05(L1 miss penalty)
    L1 miss penalty = 6 ns + .02(L2 miss penalty)
    L2 miss panelty = 20 ns + .01(60ns) = 20.6 ns.
    so the L1 miss penalty is 6 ns + . 02(20.6)ns = 6.412 ns,
    so the average access time is 1 + .05(6.412) = 1.3206 ns.

  11. Instruction    		Reservation
    Station    		Execution
    Unit    		 Issue
    Cycle    		Ex Start
    Cycle    		Ex End
    Cycle    		 Memory
    Cycle    		CDB
    cycle    		Write
    dest
    L.D    F0,8(R2)Load1ALU12234F0
    ADD.DF4,F2,F2Add1fadd2345F4
    SUB.DF6,F4,F0Add2fadd3678F6
    MUL.DF10,F2,F4Mult1fmul461011F10
    ADD.DF12,F2,F4Add3fadd58910F12
    SUB.DF14,F10,F0Add4fadd6121314F14

  12. Two functional units that can add and subtract

    Instruction    		Reservation
    Station    		Execution
    Unit    		 Issue
    Cycle    		Ex Start
    Cycle    		Ex End
    Cycle    		 Memory
    Cycle    		CDB
    cycle    		Write
    dest
    L.D    F0,8(R2)Load1ALU12234F0
    ADD.DF4,F2,F2Add1fadd12345F4
    SUB.DF6,F4,F0Add2fadd23678F6
    MUL.DF10,F2,F4Mult1fmul461011F10
    ADD.DF12,F2,F4Add3fadd15679F12
    SUB.DF14,F10,F0Add4fadd26121314F14
    Note 1: The second ADD.D does not have to wait for a functional unit.
    Note 2: This instruction cannot put its result on the CDB at cycle 8 since the CDB is busy.

  13. Cache miss it penalty 10

    Instruction    		Reservation
    Station    		Execution
    Unit    		 Issue
    Cycle    		Ex Start
    Cycle    		Ex End
    Cycle    		 Memory
    Cycle    		CDB
    cycle    		Write
    dest
    L.D    F0,8(R2)Load1ALU1221314F0
    ADD.DF4,F2,F2Add1fadd2345F4
    SUB.DF6,F4,F0Add2fadd3151617F6
    MUL.DF10,F2,F4Mult1fmul461011F10
    ADD.DF12,F2,F4Add3fadd5678F12
    SUB.DF14,F10,F0Add4fadd6171819F14
    Note 1: The first instruction memory access is delayed by 10 cycles.
    Note 2: The SUB.D cannot start executing until F0 is ready.
    Note 3: The second ADD.D no longer needs to wait for a functional unit.
    Note 4: The last instruction cannot execute until F0 and the execution unit are ready.

  14. Only 1 add reservation unit

    Instruction    		Reservation
    Station    		Execution
    Unit    		 Issue
    Cycle    		Ex Start
    Cycle    		Ex End
    Cycle    		 Memory
    Cycle    		CDB
    cycle    		Write
    dest
    L.D    F0,8(R2)Load1ALU12234F0
    ADD.DF4,F2,F2Add1fadd2345F4
    SUB.DF6,F4,F0Add1fadd6789F6
    MUL.DF10,F2,F4Mult1fmul781213F10
    ADD.DF12,F2,F4Add1fadd10111214F12
    SUB.DF14,F10,F0Add1fadd15161718F14
    Note 1: The SUB.D cannot issue until the reservation station is available after cycle 5.
    Note 2: The MUL.D cannot issue until the previous instruction does so it cannot issue until cycle 7.
    Note 3: The second ADD.D cannot issue until the reservation station is available in cycle 10.
    Note 4: The second ADD.D cannot put its resulton the CDB in cycle 13 because the CDB is busy.
    Note 5: The last instruction cannot issue until the reservation station is available.