CS 3853 Computer Architecture Recitation 12 Answers

Quiz 7a

1. 2 on 1, 4 on 1, 3 on 2, 3 on 1
2. 4 on 3, 5 on 2, 5 on 4
3. 2 and 4, 1 and 5

Quiz 7b

1. 3 on 2, 3 on 1, 5 on 3, 5 on 1, 5 on 2
2. 4 on 3, 5 on 3
3. 1 and 4, 2 and 5

Problems

1. Instruction		Reservation Station	Execution Unit	Issue Cycle	Ex Start Cycle	Ex End Cycle	Memory Cycle	CDB cycle	Write dest
   L.D	F2,8(R1)	Load1	ALU	1	2	2	3	4	F2
   ADD.D	F4,F2,F2	Add1	fadd	2	6	7		8	F4
   SUB.D	F6,F8,F8	Add2	fadd	3	4	5		6	F6
   MUL.D	F10,F4,F2	Mult1	fmul	4	9	13		14	F10
   ADD.D	F12,F2,F6	Add3	fadd	5	8	9		10	F12
   SUB.D	F14,F6,F8	Add4	fadd	6	10	11		12	F14

   
   
2. Two functional units that can add and subtract:

   Instruction		Reservation Station	Execution Unit	Issue Cycle	Ex Start Cycle	Ex End Cycle	Memory Cycle	CDB cycle	Write dest
   L.D	F2,8(R1)	Load1	ALU	1	2	2	3	4	F2
   ADD.D	F4,F2,F2	Add1	fadd1	2	5	6		7	F4
   SUB.D	F6,F8,F8	Add2	fadd2	3	4	5		6	F6
   MUL.D	F10,F4,F2	Mult1	fmul	4	8	12		13	F10
   ADD.D	F12,F2,F6	Add3	fadd1	5	7	8		9	F12
   SUB.D	F14,F6,F8	Add4	fadd2	6	7	8		10	F14

   
   
3. One functional unit for floating point (and one reservation type for floating point)

   Instruction		Reservation Station	Execution Unit	Issue Cycle	Ex Start Cycle	Ex End Cycle	Memory Cycle	CDB cycle	Write dest
   L.D	F2,8(R1)	Load1	ALU	1	2	2	3	4	F2
   ADD.D	F4,F2,F2	Fu1	fu	2	6	7		8	F4
   SUB.D	F6,F8,F8	Fu2	fu	3	4	5		6	F6
   MUL.D	F10,F4,F2	Fu3	fu	4	10	14		15	F10
   ADD.D	F12,F2,F6	Fu4	fu	5	8	9		10	F12
   SUB.D	F14,F6,F8	Fu5	fu	6	15	16		17	F14

   Note 1: Fu4 has both of its operands available in cycle 8 and waits until cycle 8 for fu to become available.
   Note 2: Fu3 has its operand available in cycle in cycle 9 but fu is not yet ready.
   Note 3: Fu5 has its operands available in cycle 8, but fu is not available.
   Note 4: Fu3 and Fu5 both become ready after cycle 9 when the fu becomes available, so Fu3 starts execution because it issued first.
   
   
4. The first instruction stalls for 6 cycles waiting for memory

   Instruction		Reservation Station	Execution Unit	Issue Cycle	Ex Start Cycle	Ex End Cycle	Memory Cycle	CDB cycle	Write dest
   L.D	F2,8(R1)	Load1	ALU	1	2	2	9	10	F2
   ADD.D	F4,F2,F2	Add1	fadd	2	11	12		13	F4
   SUB.D	F6,F8,F8	Add2	fadd	3	4	5		6	F6
   MUL.D	F10,F4,F2	Mult1	fmul	4	14	18		19	F10
   ADD.D	F12,F2,F6	Add3	fadd	5	13	14		15	F12
   SUB.D	F14,F6,F8	Add4	fadd	6	7	8		9	F14

   Note: Add1 and Add3 have their operands ready in cycle 11, so Add1 goes first because it issued first. Add3 needs to wait for fadd.
   
   
5. Assume one reservation station for each functional unit. Reservation stations are clased Load, Add, and Mult. Assume that a reservation station does not become free until the cycle after its result it put on the CDB.:

   Instruction		Reservation Station	Execution Unit	Issue Cycle	Ex Start Cycle	Ex End Cycle	Memory Cycle	CDB cycle	Write dest
   L.D	F2,8(R1)	Load	ALU	1	2	2	3	4	F2
   ADD.D	F4,F2,F2	Add	fadd	2	5	6		7	F4
   SUB.D	F6,F8,F8	Add	fadd	8	9	10		11	F6
   MUL.D	F10,F4,F2	Mult	fmul	9	10	14		15	F10
   ADD.D	F12,F2,F6	Add	fadd	12	13	14		16	F12
   SUB.D	F14,F6,F8	Add	fadd	17	18	19		20	F14

   Note 1: The first ADD.D reservies that Add when it issues so the SUB.D cannot issue until after the ADD.d uts its result on the CDB in cycle 7.
   Note 2: Since the SUB.D has not issued when ADD.D has its operands, it can start executing.
   Note 3: Even though the MUL.D has a reservation station available it has to wait for cycle 9 to issue since instructions must issue in order.
   Note 4: The second ADD.D cannot issue until SUB.D finishes and its reservation station is available.
   Note 5: The second ADD.D cannot put its result on the CDB in cycle 15 since the CDB is not available.
   
   

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