CS 3853 Computer Architecture Recitation 3 Answers Fall 2013

Quiz 3a

  1. IF, ID, EX, MEM, WB
  2. This is the ID step. The 5 and 2 are read from the IF/ID pipeline register and fed into the register file. The values of R5 and R2 are stored in the ID/EX pipeline register. The address of the destination register from the IF/ID pipeline register (3) along with some control bits are copied into the ID/EX pipeline register.
  3. old CPI = 1.25, new CPI = 1.15. Old time per instruction = 1.25, new time per instruction = 1.15 × 1.2 = 1.38, so the speedup is 1.25/1.38 = 0.9058. Note that this enhancement does not speed up the machine.

Quiz 3b

  1. IF, ID, EX, MEM, WB
  2. This is the ID step. The 2 and 3 are read from the IF/ID pipeline register and fed into the register file. The values of R2 and R3 are stored in the ID/EX pipeline register. The address of the destination register from the IF/ID pipeline register (4) along with some control bits are copied into the ID/EX pipeline register.
  3. old CPI = 1.35, new CPI = 1.21. Old time per instruction = 1.35, new time per instruction = 1.21 × 1.15 = 1.3915, so the speedup is 1.35/1.3915 = 0.97018. Note that this enhancement does not speed up the machine.

Problems

    1. 1/(.5 + .5/2) = 1/.75 = 4/3 = 1.33
    2. 1/(.1 + .9/2) = 20/11 = 1.82
    3. We can think of this as having 4 copies of A running while 1 copy of B is running.
      Program A's new exection time is 3/4 of the old, so 4 copies will take 3 units.
      Program B's new execution time is 11/20 of the old, so one copy takes 11/20 units.
      Together they take 3.55 units instead of 5 for a speedup of 5/3.55 = 1.41.
  2. EB = EA (.4 × 1.3 + .3/1.5 + .3) = 1.02 × EA, so machine A is faster and the speedup is 1.02.
    1. 1/(.5 + .5/2) = 1/.75 = 4/3 = 1.33
    2. 1/(.1 + .9/2) = 20/11 = 1.82
    3. We can think of this as having 4 copies of A running while 1 copy of B is running.
      Program A's new exection time is 3/4 of the old, so 4 copies will take 3 units.
      Program B's new execution time is 11/20 of the old, so one copy takes 11/20 units.
      Together they take 3.55 units instead of 5 for a speedup of 5/3.55 = 1.41.
    • IF: fetch the instruciton, store it in IF/ID, and add 4 to the PC
    • ID: decode the instruction, sign-extend 5 and store it in ID/EX, read R4 from the register file and store it in ID/EX, copy the instruciotn from ID/ID into ID/EX.
    • EX: Add 5 to the contents of R4 and stire the result in EX/MEM. Copy the instruction from ID/EX into EX/MEM.
    • MEM: Access the memory using the address from EX/MEM and store the result in MEM/WB. Copy the instruction from EX/MEM to MEM/WB.
    • WB: Store the memory value which was in MEM/WB into R3 in the register file.
    1. Without forwarding, R1 is not ready in the register file until the beginning of the 5th cycle of the DADD, and it is needed at the end of the second cycle of the DSUB. Two cycles of stall are needed in DSUB. No additional stalls are needed for the AND.
      With forwardings, R1 is available third cycle of DADD and is not needed until the third cycle of DSUB, so no stalls are needed.
    2. Without forwarding, this is similar to the previous example so 2 stall cycles are needed. With forwarding, R1 is available at the end of the 4th cycle of LD and is needed at the beginning of the third cycle of DSUB, so one stall cycle is needed.
  6. Move the AND instruction up one so that it is executed between the LD and the AND.