CS 3843 Computer Organization Chapter 4, Section 4.3 Trace Add

Section 4.3: Sequential Y86 Implementation - Tracing an Add Instruction

Assumptions:
  1. Instruction Memory is combinational logic.
    1. We assume it has the following instructions stored starting at location 0: 
                irmovl $11, %eax
          irmovl $7, %ecx
          addl   %eax, %ecx
          rrmovl %ecx, %edx
    2. In binary the instuction memory contains (all values in hex)
      AddressContentsComments
      0030irmovl
      01F0rB=%eax
      020B11=0x0B (little endian)
      0300second byte of 11 is 0 (little endian)
      0400third byte of 11 is 0 (little endian)
      0500fourth byte of 11 is 0 (little endian)
      0630irmovl
      07F1rB=%ecx=1
      08077=0x07 (little endian)
      0900second byte of 7 is 0 (little endian)
      0A00third byte of 7 is 0 (little endian)
      0B00fourth byte of 7 is 0 (little endian)
      0C60addl
      0D01rA=%eax=0, rB=%ecx=1
      0E20rrmovl
      0F12rA=%ecx=1, rB=%edx=2
  2. The register file acts like combinational logic when reading values.
  3. Each block of combinational logic has a fixed propgation delay of .1 (in some units)
  4. We start our trace with the addl instruction, so we have:
    PC = 0C
    %eax = 0B
    %ecx = 07
Trace:
We will need the figures that are available here or here.
  1. In Figure 4.27, coming out of the PC is 0C.
    1. Byte 0 = 60, Byte 1 = 01, the others are not used
    2. icode = 6, ifun = 0
    3. Need regids = 1, Need valC = 0
    4. valP = 0E
    5. rA = 0, rB = 1
    6. Instr valid = 1
  2. Transfer these results to Figure 4.23 and 4.28
  3. In Figure 4.28:
    1. have rA=0, rB=1, icode=6
    2. srcA=rA= 0, srcB=rB=1, dstE=rB=1
    3. dstE has no effect yet since this part is sequential
    4. valA = 0B, valB = 07
  4. Transfer these values to Figures 4.23 and 4.29
  5. In Figure 4.29
    1. valA = 0B, valB = 07, icode=6, ifun=0
    2. ALUfun = 0 (0=add, 1=sub, 2=and, 3=xor)
    3. ALU-A output = valA = 0B, ALU-B output = valB = 07
    4. SetCC output is 1
    5. CC input is 0 (all flags cleared)
    6. valE = 12 (0x0B + 0x07 = 11 + 7 = 18 = 0x12)
    7. Cnd = 0 (all flags clear)
  6. Transfer these values to Figures 4.23 and 4.28
  7. In Figure 4.23, New PC output is valP = 0E
  8. In Figure 4.28, valE = 12.
    Since dstE=rB=1, 0x12 will be stored in %ecx on the next clock cycle
  9. Also on the next clock cycle, newPC=0E will be stored in the PC
The results can be found here.

A trace of a regiser-memory move instruction can be found here.